High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Test bench to measure and investigate performance of Apache Maven project

A DAQ framework to enable complex measurement scenarios.

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.

Implementation of a Parameterized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

A slim PyQt5 Python desktop tool for real-time visualization and CSV/XLSX logging of GSV-6 / GSV-8 CAN measurement amplifiers using a dynamic device-channel tree view.

Banc de Mesure Botafumeiro - Excitation Paramétrique d'un Pendule

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Laboratory test bench for testing and evaluating high-voltage semiconductor components and materials. Features a custom 12V-to-100V Boost converter, thermal simulations, and 3D-printed enclosure.

This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.

Offline DIY water monitoring controller board for leak probes, flow sensors, buzzers, buttons, and test-bench experiments.

VLSI System Design Practice Lab

Hardware and software for a BLDC thrust and torque measurement system using STM32.

Design and manufacture a mechanical testing bench for mechanical vibration of CubeSat satellites from 1U to 3U, according to NASA-GEVS standard: GSFC-STD-7000A.

Hosting all of my ZeroBraine Lua projects

Anonymized case study: unified pneumatic + electrical test bench designed in 2020 (BTS internship), still in production 6 years later. Companion to apte-toolkit.

Automated test bench for intensive pig feeding systems, integrating PLC/HMI logic, electrical design and mechanical documentation.

VHDL assignments done at @ufms.

A VHDL implementation of Finite State Machines (FSM) and reverse engineering other hidden FSMs