FPGA synthesis tool powered by program synthesis

NTHU CS6132 Advanced Logic Synthesis Course Project (include Technology Mapping)

Coursework of NTHU CS613200 Advanced Logic Synthesis

These are verilog codes that are synthesized using open source tool yosys. We can do technology mapping using netlist, we can also estimate the area of design using info given in library.

The repository provides an optimal implementation of pebble games (standard variants as well as reversible pebble game) for arbitrary DAGs using SAT.

Solution for BDAthlon 2018: Genetic Technology Mapping.

列举基本页面渲染方式，轻松为你页面做出最优技术选型

This repository implements technology mapping using minimum cost tree-covering.