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devduttkadale1/README.md

Hi there 👋 I'm Devdutt Kadale

RTL Design Engineer | SystemVerilog | RISC-V | OpenRAM | SKY130

I am an RTL Design Engineer with experience in ASIC/FPGA RTL development, SoC integration, CDC/Lint verification, and open-source VLSI design.

Currently I am exploring open-source ASIC design, SRAM architecture, and AI-assisted semiconductor workflows using the SKY130 PDK and OpenRAM.

About Me

  • 💼 RTL Design Engineer
  • 💻 Verilog • SystemVerilog • TCL
  • 🧠 RISC-V Architecture
  • 🔬 OpenRAM & SKY130
  • 🛠️ QuestaSim • Vivado • Design Compiler • NGSpice • Magic • Netgen
  • 🌍 Based in India

GitHub Stats

Verilog SystemVerilog RISC-V OpenRAM SKY130

Technical Skills

RTL Design

  • Verilog HDL
  • SystemVerilog
  • FSM Design
  • RTL Microarchitecture
  • SoC Integration

Verification

  • CDC
  • Lint
  • STA
  • Functional Simulation

Protocols

  • I2C
  • I3C
  • UART
  • SPI
  • AXI
  • APB
  • Wishbone

Open Source ASIC

  • OpenRAM
  • SKY130
  • Xschem
  • NGSpice
  • Magic VLSI
  • Netgen

Featured Projects

Project Description
AI-Assisted 4KB SRAM Design OpenRAM, SKY130, Magic, Netgen, NGSpice, Xschem
RISC-V MYTH Workshop RV32I, TL-Verilog, Makerchip, Pipeline CPU

Connect with Me

Thanks for visiting my GitHub!

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  1. riscv-myth-workshop_devdutt riscv-myth-workshop_devdutt Public

    RISC-V | TL-Verilog | CPU Microarchitecture | MYTH Workshop Notes & Labs

    TL-Verilog 1

  2. AI-Assisted-4KB-SRAM-SKY130_devdutt_kadale AI-Assisted-4KB-SRAM-SKY130_devdutt_kadale Public

    AI-Assisted 4KB SRAM Design using OpenRAM and SKY130 PDK

    SourcePawn