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[Fix][TIRx] Handle vector access pointer addresses in C codegen - #20058

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tlopex:fix/tirx-vector-access-ptr-lowering
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[Fix][TIRx] Handle vector access pointer addresses in C codegen#20058
tlopex wants to merge 1 commit into
apache:mainfrom
tlopex:fix/tirx-vector-access-ptr-lowering

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@tlopex tlopex commented Jul 27, 2026

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This PR fixes invalid pointer arithmetic emitted by C-family codegen for vector-typed tvm_access_ptr.

A vector access pointer is lowered to address_of(BufferLoad(...)) with a Ramp index describing its lane indices. For example, Ramp(4, 1, 2) represents scalar elements [4, 5], so its address should be the address of the first lane, &A[4].

LLVM codegen already extracts Ramp::base in this case. However, CodeGenC previously passed the complete ramp to pointer arithmetic, which could generate invalid CUDA code such as:

(float*)A + make_int2(4, 5)

This PR makes CodeGenC use Ramp::base when generating the address of a vector BufferLoad. The normalized index is applied to both the direct pointer-offset path and the general GetBufferRef path.

The existing scalar-buffer plus Ramp lowering is preserved. This avoids regressions for padded vector types such as float32x3 and packed vector types such as int4x4, while making C-family codegen consistent with LLVM codegen.

Regression tests cover:

  • float32x2 C codegen.
  • Padded float32x3 LLVM codegen.
  • Packed int4x4 CUDA codegen.

Treat a Ramp-indexed BufferLoad passed to address_of as the address of its first lane, matching LLVM codegen. Keep vector access pointer lowering in scalar element units so padded and packed vector dtypes retain their existing semantics.
@apache apache deleted a comment from gemini-code-assist Bot Jul 27, 2026
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